The present invention relates to the cooling of a semiconductor device, and more particularly, to a semiconductor device having an embedded heatsink.
Within the integrated circuit industry there is a continuing effort to increase integrated circuit speed as well as device density. As a result of these efforts, there is a trend towards using flip chip technology when packaging complex high speed integrated circuits. Flip chip technology is also known as controlled collapse chip connection (C4) technology. In C4 technology, the integrated circuit die is flipped upside down. This is opposite to how integrated circuits are generally packaged today using wire bond technology. By flipping the integrated circuit die upside down, ball bonds may be used to provide direct electrical connections from the bond pads of the die directly to a corresponding set of pads on a package.
In the following discussion reference will be made to a number of drawings. The drawings are provided for descriptive purposes only and are not drawn to scale.
FIG. 1A illustrates a C4 mounted integrated circuit die 102 that is electrically coupled to a package substrate 120 by ball bonds 116. Die 102 includes a semiconductor substrate 104 that has a frontside surface 114 and a backside surface 112. The active regions 106 and 108 of the integrated circuit are formed from the frontside surface 114 of the of the semiconductor substrate 104. Because the bond pads of integrated circuit device 102 are located adjacent the frontside surface 114 of the device, the die must be flipped upside down so that it may be attached to package substrate 120.
With microprocessor core frequencies climbing into the gigahertz range, one of the major concerns in microprocessor performance is thermal management. There are well known reliability and performance concerns with very high power parts, as the junction temperature must be maintained below certain temperature limits to ensure long life of the part and also to achieve reasonable transistor performance. Specifically, there is a need to address localized cooling of very high power circuit areas on the chip.
FIG. 1B illustrates a prior art approach to dissipating heat from a C4 mounted integrated circuit device. Heat is removed from the backside surface 112 of device 102 by passing an air flow 140 over a finned heatsink 130 that is thermally coupled to the backside surface 112. In some instances, heat is dissipated from device 102 by attaching a thermally conductive heat slug to backside surface 112 and thermally coupling the heat slug to a heatsink. In other instances, the heat slug may be thermally coupled to a heat spreading plate by a heat pipe or some other low resistance path.
The semiconductor substrate 104 is typically made of silicon, or other types of semiconductor materials. These materials are capable of conducting a certain amount of heat which permits heat to be conducted from the transistor level where it is generated, through the semiconductor substrate 104, and then into the heatsink 130. However, due to non-uniform heat dissipation between different regions of the integrated circuit, there can still be local xe2x80x9chot spotsxe2x80x9d on the die in which the junction temperatures in one region of the die can be higher than in other regions of die. Local hot spots can lead to reduced long-term reliability of the integrated circuit, as degradation mechanisms such as electromigration are increased at elevated temperatures. Furthermore, the speed performance of the integrated circuit is reduced at higher temperatures due to decreased electron mobility in the transistors.
What is needed is a method and an apparatus for removing heat from an integrated circuit in a manner that minimizes temperature gradients across the integrated circuit.